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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS12014-A
FLAT-BASE TYPE
INSULATED TYPE
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART.
off
N-side IGBT Current
N-side FWDi Current
V CIN
V(hold)
I C
(V S )
V C
V CL
on
on
off
0
+I CL
0
Ref
0
off
on
t(hold)
Delay time
td(read)
–I CL
Fig. 9 START-UP SEQUENCE
Normally at start-up, Fo and CL output signals will be pulled-up
High to V DL voltage (OFF level); however, F O1 output may fall to
Low (ON) level at the instant of the first ON input pulse to an N-Side
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
IGBT. This can happen particularly when the boot-strap capacitor is
of large size. F O1 resetting sequence (together with the boot-strap
charging sequence) is explained in the following graph
5.1k ?
V DL (5V)
ASIPM
R
U P ,V P ,W P ,U N ,V N ,W N ,Br
DC-Bus voltage
Control voltage supply
Boot-strap voltage
V PN 0
V DH, DL 0
V DB
0
PWM starts
a)
b)
CPU
R
10k ?
F O1 ,F O2 ,F O3 ,CL
CU,CV,CW
N-Side input signal
V CIN(N)
on
0.1nF
0.1nF
GND(Logic)
P-Side input signal
Brake input signal
V CIN(P) on
V CIN(Br) on
F O 1 output signal
F OI
on
a) Boot-strap charging scheme :
Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20 μ s number of pulses =10 ~ 500 de-
pending on the boot-strap capacitor size)
b) F O1 resetting sequence:
Apply ON signals to the following input pins : Br → Un/Vn/Wn → Up/Vp/Wp in that order.
Jan. 2000
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